LEADER 00000nam  2200301   4500 
001    AAI3194284 
005    20100608105210.5 
008    100608s2005    ||||||||||||||||| ||eng d 
020    9780542377624 
035    (UMI)AAI3194284 
040    UMI|cUMI 
100 1  Ahn, Gil Cho 
245 10 Design techniques for low-voltage and low-power analog-to-
       digital converters 
300    89 p 
500    Source: Dissertation Abstracts International, Volume: 66-
       10, Section: B, page: 5570 
500    Adviser:  Un-Ku Moon 
502    Thesis (Ph.D.)--Oregon State University, 2005 
520    With the ever-increasing demand for portable devices used 
       in applications such as wireless communication, mobile 
       computing, consumer electronics, etc., the scaling of the 
       CMOS process to deep submicron dimensions becomes more 
       important to achieve low-cost, low-power and high-
       performance digital systems. However, this downscaling 
       also requires similar shrinking of the supply voltage to 
       insure device reliability. Even though the largest amount 
       of signal processing is done in the digital domain, the on
       -chip analog-to-digital interface circuitry (analog-to-
       digital and digital-to-analog converters) is an important 
       functional block in the system. These converters are also 
       required to operate with low-voltage supply. In this 
       thesis, design techniques for low-voltage and low-power 
       analog-to-digital converters are proposed. The specific 
       research contributions of this work include (1) 
       introduction of a new low-voltage switching technique for 
       switched capacitor circuit design, (2) development of low-
       voltage and low-distortion delta-sigma modulator, (3) 
       development of low-voltage switched-capacitor multiplying 
       digital-to-analog converter (MDAC), (4) a new architecture
       for the low-power Nyquist rate pipelined ADC design. These
       design techniques enable the implementation of low-voltage
       and low-power CMOS analog-to-digital converters. To 
       demonstrate the proposed design techniques, a 0.6 V, 82 dB,
       2-2 cascaded audio delta-sigma ADC, a 0.9 V, 10-bit, 20MS/
       s CMOS pipelined ADC and a 2.4 V, 12-bit, 10MS/s CMOS 
       pipelined ADC were implemented in standard CMOS processes 
590    School code: 0172 
650  4 Engineering, Electronics and Electrical 
690    0544 
710 2  Oregon State University 
773 0  |tDissertation Abstracts International|g66-10B 
856 40 |uhttp://pqdd.sinica.edu.tw/twdaoapp/servlet/