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Author Vyvoda, Michael Andrew
Title Surface evolution during integrated circuit processing
book jacket
Descript 203 p
Note Source: Dissertation Abstracts International, Volume: 60-05, Section: B, page: 2246
Chair: David B. Graves
Thesis (Ph.D.)--University of California, Berkeley, 1999
Experimental and modeling studies of surface evolution during integrated circuit (IC) processing were performed in order to obtain a clearer understanding of important phenomena in effect during small feature development. Experiments were conducted in a commercial plasma etching system, and a reactor modeling---feature evolution simulation approach was taken in order to explain the formation of various anomalous microfeatures. Similarly, metal deposition simulations were performed to examine feature evolution during ionized physical vapor deposition (I-PVD)
During crystalline silicon etching in a commercial high density inductively-coupled plasma system, we found that when pure Cl2 was the etchant feedgas, deep and localized "microtrenches" formed near trench sidewalls at 10 mTorr reactor pressure, an undesirable feature that can compromise IC device yields. Raising the RF-bias power had no effect on microtrench growth at 10 mTorr. However, when pure HBr was used with all other reactor settings held constant, silicon trenches evolved with completely flat bottoms. Isolated line profiles show that, in the case of HBr etching, broad but shallow microtrenches do in fact form. These broad microtrenches overlap when etching high-aspect ratio trenches, resulting in flat trench bottoms. Separately, when the reactor pressure was lowered to 2 mTorr when etching with a Cl 2 plasma, the microtrenches changed in character from narrow and localized to triangular, with widths of approximately one-half of the lateral trench dimension. When the RF-bias power was raised at 2 mTorr, these triangular microtrenches disappeared
A combined plasma reactor - feature evolution simulation was developed to examine the growth of both localized and triangular microtrenches, and their disappearance upon changing etchant feedgas (at 10 mTorr) or bias power (at 2 mTorr). The plasma reactor model predicts fluxes of important species impacting the wafer surface, and the feature evolution model solves for the surface topography as a function of time. By using a broad scattering distribution of ions reflected from feature sidewalls, the broad microtrench growth seen when etching isolated lines with HBr plasmas was reproduced, and silicon trenches evolved with flat bottoms due to overlapping, broad microtrenches. Furthermore, a segment of the feature evolution simulation that allows for differential charging of the insulating masking material, and subsequent trajectory deflection of incident energetic ions, suggests that the more triangular microtrenches seen at 2 mTorr form due to focusing of ions from the plasma bulk. When the RF-bias power was raised, the higher-energy ions were less susceptible to trajectory deflection, and the triangular microtrenches did not form
Finally, feature evolution simulations of copper seed layer deposition were conducted. A copper seed layer is a thin film used to provide for an electrodeposition adhesion layer during copper interconnect metallization. We show that, in order to predict details of the evolution of this layer with sufficient accuracy, ion scattering and sputtering distributions calculated using molecular dynamics simulations are necessary. This is especially true in the limit of high ion energies and/or high ion-neutral flux ratio
School code: 0028
Host Item Dissertation Abstracts International 60-05B
Subject Engineering, Chemical
Engineering, Electronics and Electrical
Alt Author University of California, Berkeley
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