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Author Li, Richard C
Title RF Circuit Design
Imprint Somerset : John Wiley & Sons, Incorporated, 2012
©2012
book jacket
Edition 2nd ed
Descript 1 online resource (862 pages)
text txt rdacontent
computer c rdamedia
online resource cr rdacarrier
Series Information and Communication Technology Series, Ser. ; v.102
Information and Communication Technology Series, Ser
Note Intro -- RF CIRCUIT DESIGN -- CONTENTS -- PREFACE TO THE SECOND EDITION -- PART 1 DESIGN TECHNOLOGIES AND SKILLS -- 1 DIFFERENCE BETWEEN RF AND DIGITAL CIRCUIT DESIGN -- 1.1 Controversy -- 1.1.1 Impedance Matching -- 1.1.2 Key Parameter -- 1.1.3 Circuit Testing and Main Test Equipment -- 1.2 Difference of RF and Digital Block in a Communication System -- 1.2.1 Impedance -- 1.2.2 Current Drain -- 1.2.3 Location -- 1.3 Conclusions -- 1.4 Notes for High-Speed Digital Circuit Design -- Further Reading -- Exercises -- Answers -- 2 REFLECTION AND SELF-INTERFERENCE -- 2.1 Introduction -- 2.2 Voltage Delivered from a Source to a Load -- 2.2.1 General Expression of Voltage Delivered from a Source to a Load when << y/4 so that Td 0 -- 2.2.2 Additional Jitter or Distortion in a Digital Circuit Block -- 2.3 Power Delivered from a Source to a Load -- 2.3.1 General Expression of Power Delivered from a Source to a Load when << y/4 so that Td 0 -- 2.3.2 Power Instability -- 2.3.3 Additional Power Loss -- 2.3.4 Additional Distortion -- 2.3.5 Additional Interference -- 2.4 Impedance Conjugate Matching -- 2.4.1 Maximizing Power Transport -- 2.4.2 Power Transport without Phase Shift -- 2.4.3 Impedance Matching Network -- 2.4.4 Necessity of Impedance Matching -- 2.5 Additional Effect of Impedance Matching -- 2.5.1 Voltage Pumped up by Means of Impedance Matching -- 2.5.2 Power Measurement -- Appendices -- 2.A.1 VSWR and Other Reflection and Transmission Coefficients -- 2.A.2 Relationships between Power (dBm), Voltage (V), and Power (W) -- Reference -- Further Reading -- Exercises -- Answers -- 3 IMPEDANCE MATCHING IN THE NARROW-BAND CASE -- 3.1 Introduction -- 3.2 Impedance Matching by Means of Return Loss Adjustment -- 3.2.1 Return Loss Circles on the Smith Chart -- 3.2.2 Relationship between Return Loss and Impedance Matching
3.2.3 Implementation of an Impedance Matching Network -- 3.3 Impedance Matching Network Built by One Part -- 3.3.1 One Part Inserted into Impedance Matching Network in Series -- 3.3.2 One Part Inserted into the Impedance Matching Network in Parallel -- 3.4 Impedance Matching Network Built by Two Parts -- 3.4.1 Regions in a Smith Chart -- 3.4.2 Values of Parts -- 3.4.3 Selection of Topology -- 3.5 Impedance Matching Network Built By Three Parts -- 3.5.1 "" Type and "T" Type Topologies -- 3.5.2 Recommended Topology -- 3.6 Impedance Matching When ZS Or ZL Is Not 50 _ -- 3.7 Parts In An Impedance Matching Network -- Appendices -- 3.A.1 Fundamentals of the Smith Chart -- 3.A.2 Formula for Two-Part Impedance Matching Network -- 3.A.3 Topology Limitations of the Two-Part Impedance Matching Network -- 3.A.4 Topology Limitation of Three Parts Impedance Matching Network -- 3.A.5 Conversion between _ and T Type Matching Network -- 3.A.6 Possible _ and T Impedance Matching Networks -- Reference -- Further Reading -- Exercises -- Answers -- 4 IMPEDANCE MATCHING IN THE WIDEBAND CASE -- 4.1 Appearance of Narrow and Wideband Return Loss on a Smith Chart -- 4.2 Impedance Variation Due to the Insertion of One Part Per Arm or Per Branch -- 4.2.1 An Inductor Inserted into Impedance Matching Network in Series -- 4.2.2 A Capacitor Inserted into Impedance Matching Network in Series -- 4.2.3 An Inductor Inserted into Impedance Matching Network in Parallel -- 4.2.4 A Capacitor Inserted into Impedance Matching Network in Parallel -- 4.3 Impedance Variation Due to the Insertion of Two Parts Per Arm or Per Branch -- 4.3.1 Two Parts Connected in Series to Form One Arm -- 4.3.2 Two Parts Are Connected in Parallel to Form One Branch -- 4.4 Partial Impedance Matching for an IQ (in Phase Quadrature) Modulator in a UWB (Ultra Wide Band) System -- 4.4.1 Gilbert Cell
4.4.2 Impedances of the Gilbert Cell -- 4.4.3 Impedance Matching for LO, RF, and IF Ports Ignoring the Bandwidth -- 4.4.4 Wide Bandwidth Required in a UWB (Ultra Wide Band) System -- 4.4.5 Basic Idea to Expand the Bandwidth -- 4.4.6 Example 1: Impedance Matching in IQ Modulator Design for Group 1 in a UWB System -- 4.4.7 Example 2: Impedance Matching in IQ Modulator Design for Group 3 + Group 6 in a UWB System -- 4.5 Discussion of Passive Wideband Impedance Matching Network -- 4.5.1 Impedance Matching for the Gate of a MOSFET Device -- 4.5.2 Impedance Matching for the Drain of a MOSFET Device -- Further Reading -- Exercises -- Answers -- 5 IMPEDANCE AND GAIN OF A RAW DEVICE -- 5.1 Introduction -- 5.2 Miller Effect -- 5.3 Small-Signal Model of a Bipolar Transistor -- 5.4 Bipolar Transistor with CE (Common Emitter) Configuration -- 5.4.1 Open-Circuit Voltage Gain Av,CE of a CE Device -- 5.4.2 Short-Circuit Current Gain bCE and Frequency Response of a CE Device -- 5.4.3 Primary Input and Output Impedance of a CE (common emitter) device -- 5.4.4 Miller's Effect in a Bipolar Transistor with CE Configuration -- 5.4.5 Emitter Degeneration -- 5.5 Bipolar Transistor with CB (Common Base) Configuration -- 5.5.1 Open-Circuit Voltage Gain Av,CB of a CB Device -- 5.5.2 Short-Circuit Current Gain bCG and Frequency Response of a CB Device -- 5.5.3 Input and Output Impedance of a CB Device -- 5.6 Bipolar Transistor with CC (Common Collector) Configuration -- 5.6.1 Open-Circuit Voltage Gain Av,CC of a CC Device -- 5.6.2 Short-Circuit Current Gain bCC and Frequency Response of the Bipolar Transistor with CC Configuration -- 5.6.3 Input and Output Impedance of a CC Device -- 5.7 Small-Signal Model of a MOSFET -- 5.8 Similarity Between a Bipolar Transistor and a MOSFET -- 5.8.1 Simplified Model of CS Device -- 5.8.2 Simplified Model of CG Device
5.8.3 Simplified Model of CD Device -- 5.9 MOSFET with CS (Common Source) Configuration -- 5.9.1 Open-Circuit Voltage Gain Av,CS of a CS Device -- 5.9.2 Short-Circuit Current Gain bCS and Frequency Response of a CS Device -- 5.9.3 Input and Output Impedance of a CS Device -- 5.9.4 Source Degeneration -- 5.10 MOSFET with CG (Common Gate) Configuration -- 5.10.1 Open-Circuit Voltage Gain of a CG Device -- 5.10.2 Short-Circuit Current Gain and Frequency Response of a CG Device -- 5.10.3 Input and Output Impedance of a CG Device -- 5.11 MOSFET with CD (Common Drain) Configuration -- 5.11.1 Open-Circuit Voltage Gain Av,CD of a CD Device -- 5.11.2 Short-Circuit Current Gain bCD and Frequency Response of a CD Device -- 5.11.3 Input and Output Impedance of a CD Device -- 5.12 Comparison of Transistor Configuration of Single-stage Amplifiers with Different Configurations -- Further Reading -- Exercises -- Answers -- 6 IMPEDANCE MEASUREMENT -- 6.1 Introduction -- 6.2 Scalar and Vector Voltage Measurement -- 6.2.1 Voltage Measurement by Oscilloscope -- 6.2.2 Voltage Measurement by Vector Voltmeter -- 6.3 Direct Impedance Measurement by a Network Analyzer -- 6.3.1 Direction of Impedance Measurement -- 6.3.2 Advantage of Measuring S Parameters -- 6.3.3 Theoretical Background of Impedance Measurement by S Parameters -- 6.3.4 S Parameter Measurement by Vector Voltmeter -- 6.3.5 Calibration of the Network Analyzer -- 6.4 Alternative Impedance Measurement by Network Analyzer -- 6.4.1 Accuracy of the Smith Chart -- 6.4.2 Low- and High-Impedance Measurement -- 6.5 Impedance Measurement Using a Circulator -- Appendices -- 6.A.1 Relationship Between the Impedance in Series and in Parallel -- Further Reading -- Exercises -- Answers -- 7 GROUNDING -- 7.1 Implication of Grounding -- 7.2 Possible Grounding Problems Hidden in a Schematic
7.3 Imperfect or Inappropriate Grounding Examples -- 7.3.1 Inappropriate Selection of Bypass Capacitor -- 7.3.2 Imperfect Grounding -- 7.3.3 Improper Connection -- 7.4 'Zero' Capacitor -- 7.4.1 What is a Zero Capacitor -- 7.4.2 Selection of a Zero Capacitor -- 7.4.3 Bandwidth of a Zero Capacitor -- 7.4.4 Combined Effect of Multi-Zero Capacitors -- 7.4.5 Chip Inductor is a Good Assistant -- 7.4.6 Zero Capacitor in RFIC Design -- 7.5 Quarter Wavelength of Microstrip Line -- 7.5.1 A Runner is a Part in RF Circuitry -- 7.5.2 Why Quarter Wavelength is so Important -- 7.5.3 Magic Open-Circuited Quarter Wavelength of Microstrip Line -- 7.5.4 Testing for Width of Microstrip Line with Specific Characteristic Impedance -- 7.5.5 Testing for Quarter Wavelength -- Appendices -- 7.A.1 Characterizing of Chip Capacitor and Chip Inductor by Means of S21 Testing -- 7.A.2 Characterizing of Chip Resistor by Means of S11 of S22 Testing -- Reference -- Further Reading -- Exercises -- Answers -- 8 EQUIPOTENTIALITY AND CURRENT COUPLING ON THE GROUND SURFACE -- 8.1 Equipotentiality on the Ground Surface -- 8.1.1 Equipotentiality on the Grounded Surface of an RF Cable -- 8.1.2 Equipotentiality on the Grounded Surface of a PCB -- 8.1.3 Possible Problems of a Large Test PCB -- 8.1.4 Coercing Grounding -- 8.1.5 Testing for Equipotentiality -- 8.2 Forward and Return Current Coupling -- 8.2.1 Indifferent Assumption and Great Ignore -- 8.2.2 Reduction of Current Coupling on a PCB -- 8.2.3 Reduction of Current Coupling in an IC Die -- 8.2.4 Reduction of Current Coupling between Multiple RF Blocks -- 8.2.5 A Plausible System Assembly -- 8.3 PCB or IC Chip with Multimetallic Layers -- Further Reading -- Exercises -- Answers -- 9 LAYOUT -- 9.1 Difference in Layout between an Individual Block and a System -- 9.2 Primary Considerations of a PCB -- 9.2.1 Types of PCBs
9.2.2 Main Electromagnetic Parameters
Summarizes the schemes and technologies in RF circuit design, describes the basic parameters of an RF system and the fundamentals of RF system design, and presents an introduction of the individual RF circuit block design. Forming the backbone of today's mobile and satellite communications networks, radio frequency (RF) components and circuits are incorporated into everything that transmits or receives a radio wave, such as mobile phones, radio, WiFi, and walkie talkies. RF Circuit Design, Second Edition immerses practicing and aspiring industry professionals in the complex world of RF design. Completely restructured and reorganized with new content, end-of-chapter exercises, illustrations, and an appendix, the book presents integral information in three complete sections: Part One explains the different methodologies between RF and digital circuit design and covers voltage and power transportation, impedance matching in narrow-band case and wide-band case, gain of a raw device, measurement, and grounding. It also goes over equipotentiality and current coupling on ground surface, as well as layout and packaging, manufacturability of product design, and radio frequency integrated circuit (RFIC). Part Two includes content on the main parameters and system analysis in RF circuit design, the fundamentals of differential pair and common-mode rejection ratio (CMRR), Balun, and system-on-a-chip (SOC). Part Three covers low-noise amplifier (LNA), power amplifier (PA), voltage-controlled oscillator (VCO), mixers, and tunable filters. RF Circuit Design, Second Edition is an ideal book for engineers and managers who work in RF circuit design and for courses in electrical or electronic engineering
Description based on publisher supplied metadata and other sources
Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2020. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries
Link Print version: Li, Richard C. RF Circuit Design Somerset : John Wiley & Sons, Incorporated,c2012 9781118128497
Subject Electronic circuit design.;Radio circuits -- Design and construction.;Radio frequency
Electronic books
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