MARC 主機 00000pam  2200000 a 4500 
001       90037022 
005    19900905081014.8 
008    900417s1990    maua     b    101 0 eng   
020    0792390741 
040    DLC|cDLC|dDLC|dAS|dIIS 
050 00 TK7895.M4|bC33 1990 
082 00 004.5|220 
245 00 Cache and interconnect architectures in multiprocessors /
       |c[edited] by Michel Dubois and Shreekant S. Thakkar 
260    Boston :|bKluwer Academic Publishers,|cc1990 
300    xii, 276 p. :|bill. ;|c25 cm 
500    Papers presented at a workshop titled Cache and 
       Interconnect Architectures in Multiprocessors, held in 
       Eilat, Israel, May 25-26, 1989 
504    Includes bibliographical references and index 
650  0 Cache memory|xCongresses 
650  0 Multiprocessors|xCongresses 
650  0 Computer network architectures|xCongresses 
650  7 Multiprocessors|2iis 
650  7 Protocols|2iisf 
650  7 Cache memories|2iis 
700 1  Dubois, Michel,|d1953- 
700 1  Thakkar, S. S 
740 01 Interconnect architectures in multiprocessors 
館藏地 索書號 處理狀態 OPAC 訊息 條碼
 資訊所圖書室圖書區  C1.2 C119    在架上    30330000078498