MARC 主機 00000nam  2200337   4500 
001    AAI3388743 
005    20100927084923.5 
008    100927s2009    ||||||||||||||||| ||eng d 
020    9781109567519 
035    (UMI)AAI3388743 
040    UMI|cUMI 
100 1  Asaduzzaman, Abu 
245 10 Cache optimization for real-time embedded systems 
300    135 p 
500    Source: Dissertation Abstracts International, Volume: 71-
       01, Section: B, page: 0517 
500    Adviser:  Imad Mahgoub 
502    Thesis (Ph.D.)--Florida Atlantic University, 2009 
520    Cache memory is used, in most single-core and multi-core 
       processors, to improve performance by bridging the speed 
       gap between the main memory and CPU. Even though cache 
       increases performance, it poses some serious challenges 
       for embedded systems running real-time applications. Cache
       introduces execution time unpredictability due to its 
       adaptive and dynamic nature and cache consumes vast amount
       of power to be operated. Energy requirement and execution 
       time predictability are crucial for the success of real-
       time embedded systems. Various cache optimization schemes 
       have been proposed to address the performance, power 
       consumption, and predictability issues. However, currently
       available solutions are not adequate for real-time 
       embedded systems as they do not address the performance, 
       power consumption, and execution time predictability 
       issues at the same time. Moreover, existing solutions are 
       not suitable for dealing with multi-core architecture 
520    In this dissertation, we develop a methodology through 
       cache optimization for real-time embedded systems that can
       be used to analyze and improve execution time 
       predictability and performance/power ratio at the same 
       time. This methodology is effective for both single-core 
       and multi-core systems. First, we develop a cache modeling
       and optimization technique for single-core systems to 
       improve performance. Then, we develop a cache modeling and
       optimization technique for multi-core systems to improve 
       performance/power ratio. We develop a cache locking scheme
       to improve execution time predictability for real-time 
       systems. We introduce Miss Table (MT) based cache locking 
       scheme with victim cache (VC) to improve predictability 
       and performance/power ratio. MT holds information about 
       memory blocks, which may cause more misses if not locked, 
       to improve cache locking performance. VC temporarily 
       stores the victim blocks from level-1 cache to improve 
       cache hits. In addition, MT is used to improve cache 
       replacement performance and VC is used to improve cache 
       hits by supporting stream buffering. We also develop 
       strategies to generate realistic workload by 
       characterizing applications to simulate cache optimization
       and cache locking schemes. Popular MPEG4, H.264/AVC, FFT, 
       MI, and DFT applications are used to run the simulation 
       programs Simulation results show that newly introduced 
       Miss Table based cache locking scheme with victim cache 
       significantly improves the predictability and performance/
       power ratio. In this work, a reduction of 33% in mean 
       delay per task and a reduction of 41% in total power 
       consumption are achieved by using MT and VCs while locking
       25% of level-2 cache size in an 4-core system. It is also 
       observed that execution time predictability can be 
       improved by avoiding more than 50% cache misses while 
       locking one-fourth of the cache size 
590    School code: 0119 
650  4 Engineering, Computer 
650  4 Computer Science 
690    0464 
690    0984 
710 2  Florida Atlantic University 
773 0  |tDissertation Abstracts International|g71-01B 
856 40 |u