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作者 Cheang, Sin Man
書名 Genetic parallel programming
國際標準書號 9780542235290
book jacket
說明 237 p
附註 Source: Dissertation Abstracts International, Volume: 66-07, Section: B, page: 3788
Supervisors: Kwong Sak Leung; Kin Hong Lee
Thesis (Ph.D.)--The Chinese University of Hong Kong (People's Republic of China), 2005
This thesis investigates the design and implementation of a novel linear-structured Genetic Programming (GP) paradigm, Genetic Parallel Programming (GPP), in which a parallel architecture, Multi-Arithmetic-Logic-Unit Processor (MAP) is employed. The MAP is a MIMD, general-purpose register machine that can be implemented on modern Field Programmable Gate Arrays so that genetic parallel programs can be evaluated at high speed. Based on the parallel architecture of MAP, GPP evolves genetic programs in parallel form. This thesis presents a number of benchmark problems. The evolved solution programs are precise and compact
For human programmers, writing parallel programs is more difficult than writing sequential programs. However, an accelerating phenomenon in GPP, the GPP accelerating phenomenon, is observed. Experimental results show that GPP evolves parallel programs with less computational effort than that of their sequential counterparts. This creates a new approach to evolving a feasible problem solution program in parallel form and then serializes it into a sequential form if required. Since serialization is mechanical and its processing time is linear with respect to the size of the parallel program, the total learning time can be reduced significantly
To evolve parallel programs effectively and efficiently, this thesis also investigates different genetic operators to assist the evolution. These operators include Dynamic Sample Weighting (DSW), dual-phase fitness functions and special types of mutation for parallel programs. Since the samples in a training set are captured directly from a real-world system, the distribution of these samples can be extremely biased. DSW adjusts the weights of training samples dynamically according to their past frequency of hits. Experimental results show that DSW boosts the evolutionary performance significantly
To demonstrate the applicability of GPP, two application systems have been developed: (1) GPP Data Classification System (GPP-Classifier); and (2) GPP Logic Circuit Synthesizer (GPPLCS). The GPP-Classifier evolves MAP programs to classify data records in a database. The GPPLCS synthesizes combinational logic circuits directly from a truth table with different logic gates or RAM-based lookup-tables. High performance logic circuits are evolved and both their gate counts and propagation gate delays are less than that of the conventional designs
School code: 1307
DDC
Host Item Dissertation Abstracts International 66-07B
主題 Computer Science
0984
Alt Author The Chinese University of Hong Kong (People's Republic of China)
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