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作者 Ghoneima, Maged M
書名 Improving the bit-rate, noise performance and power dissipation of on-chip buses
國際標準書號 9780542623301
book jacket
說明 325 p
附註 Source: Dissertation Abstracts International, Volume: 67-03, Section: B, page: 1598
Adviser: Yehea Ismail
Thesis (Ph.D.)--Northwestern University, 2006
Today's System-On-Chip (SOC) devices are targeting complex applications, where there is a need for significant amount of computing power and data transfer. This implies that the number of on-chip modules will increase, and so will the number of on chip buses connecting these modules. With the continuous scaling of technology, increased die area and faster clock speeds, the delay and power dissipation of on-chip buses are becoming one of the main bottlenecks in current high-performance SoC design
The delay, noise and energy dissipation of long on-chip buses are a strong function of the coupling capacitance between the wires. As the technology is scaled, the lateral component of interconnect capacitance significantly grows to dominate the total interconnect capacitance due to reduction in wire pitch and the increase in the interconnects' aspect ratio
The focus of this dissertation is to develop circuit techniques to reduce the effective coupling capacitance between coupled interconnects in order to reduce the power dissipation, induced noise, and delay of on-chip buses. A low power coupling-based encoding scheme is proposed to minimize the power consumption of on-chip buses by reducing the relative switching activity between adjacent bus lines. A new positioning scheme for interleaved repeaters on bidirectional buses is also introduced to provide better propagation delay and noise performance than the commonly used midway positioning scheme. Another proposed low-power bus scheme, DDL, introduces dynamic relative delays only between oppositely switching adjacent lines to reduce the capacitive coupling component of delay and energy dissipation. A Source-Synchronous Multi-Cycle Bus (SSMCB) is also proposed which is scalable, appropriate for communication between different clock domains, low-power and improves the tolerance to process variations. Furthermore, the concept of implementing serial-links on-chip was proposed to fully utilize the interconnect bandwidth. This efficiently uses scarce interconnect resources such as in the many-core platform and the for "Thru-Silicon Vias " in 3D die stacks. Another proposed technique is the active shielding technique, which replaces the passive shields in the conventional shielding scheme with active shields to further reduce the bus power dissipation. Many industrial and experimental results are also presented throughout the dissertation in support of the presented theory
School code: 0163
DDC
Host Item Dissertation Abstracts International 67-03B
主題 Engineering, Electronics and Electrical
0544
Alt Author Northwestern University
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