MARC 主機 00000nam  2200373   4500 
001    AAI3160715 
005    20051216105417.5 
008    051216s2005                        eng d 
020    0496939637 
035    (UnM)AAI3160715 
040    UnM|cUnM 
100 1  Yu, Haobo 
245 10 Software synthesis for System-on-Chip 
300    147 p 
500    Source: Dissertation Abstracts International, Volume: 66-
       01, Section: B, page: 0383 
500    Chairs:  Daniel D. Gajski; Rainer Domer 
502    Thesis (Ph.D.)--University of California, Irvine, 2005 
520    Raising the level of abstraction to system level promises 
       to enable faster exploration of the design space at early 
       stages. While there are some approaches to synthesis 
       hardware from the system models, today it is still a 
       common practice to implement embedded soft ware manually 
       on a prototype board during the last stage of system 
       design. It is a tedious and error prone job. To speed up 
       system design, developing software and hardware at the 
       same time from system models seems to be the right 
       solution, which means closing the gap between the high 
       level models used for exploration and low level software 
       implementation 
520    We propose software synthesis as a solution to the problem
       of generating embedded software for System-on-Chip (SoC). 
       Software synthesis is the translation process from a high 
       level functionality specification to the low level 
       software implementation. Several well defined design steps
       and design models are introduced in the software synthesis
       methodology. Starting from a HW/SW partitioned system 
       model, the software part of the design is brought down to 
       a binary implementation through scheduling refinement, 
       code generation and  RTOS targeting steps 
520    In the software synthesis flow, from the input HW/SW 
       partitioned model to the final cycle accurate 
       implementation model, we proposed two intermediate system 
       models for software generation:  multi-task model and C 
       model. These four models breaks the embedded software 
       design gap into a set of successive synthesis steps. 
       Furthermore, design decisions and algorithms for each 
       synthesis step have been defined such that model 
       refinement and decision making can be automated while 
       supporting a wide range of HW/SW partitions and target 
       implementations 
520    The software synthesis flow and algorithms were developed 
       and integrated into the System-on-Chip design Environment 
       (SCE). Experiments using several industrial-strength 
       examples demonstrate the feasibility and benefits of using
       software synthesis in system design 
590    School code: 0030 
590    DDC 
650  4 Computer Science 
650  4 Engineering, Electronics and Electrical 
690    0984 
690    0544 
710 20 University of California, Irvine 
773 0  |tDissertation Abstracts International|g66-01B 
856 40 |uhttp://pqdd.sinica.edu.tw/twdaoapp/servlet/
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