Author Xie, Yuan, 1973-, author
Title Die-stacking architecture / Yuan Xie, Jishen Zhao
Imprint San Rafael, California (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool, 2015
book jacket
Descript 1 online resource (xiii, 113 pages) : illustrations
text rdacontent
electronic isbdmedia
online resource rdacarrier
Series Synthesis lectures on computer architecture, 1935-3243 ; # 31
Synthesis digital library of engineering and computer science
Synthesis lectures in computer architecture ; # 31. 1935-3243
Note Part of: Synthesis digital library of engineering and computer science
Includes bibliographical references (pages 99-111)
1. 3D integration technology -- 1.1 3D integrated circuits vs. 3D packaging -- 1.2 Different process technologies for 3D ICs -- 1.3 The impact of 3D technology on 3D microprocessor partitioning --
2. Benefits of 3D integration -- 2.1 Wire length reduction -- 2.2 Memory bandwidth improvement -- 2.3 Heterogenous integration -- 2.4 Cost-effective architecture --
3. Fine-granularity 3D processor design -- 3.1 3D cache partitioning -- 3.1.1 3D cache partitioning strategies -- 3.1.2 Design exploration using 3DCacti -- 3.2 3D Partitioning for logic blocks --
4. Coarse-granularity 3D processor design -- 4.1 3D Caches stacking -- 4.2 3D Main memory stacking -- 4.3 3D On-chip stacked memory: cache or main memory? -- 4.3.1 On-chip main memory -- 4.3.2 3D-stacked LLC -- 4.3.3 Dynamic approach -- 4.4 PicoServer --
5. 3D GPU architecture -- 5.1 3D-stacked GPU memory -- 5.2 3D-stacked GPU processor --
6. 3D network-on-chip -- 6.1 3D NoC router design -- 6.2 3D NoC topology design -- 6.3 3D optical NoC design -- 6.4 Impact of 3D technology on NoC designs --
7. Thermal analysis and thermal-aware design -- 7.1 Thermal analysis -- 7.2 Thermal-aware floorplanning for 3D processors -- 7.3 Thermal-herding: thermal-aware architecture design --
8. Cost analysis for 3D ICs -- 8.1 3D cost model -- 8.2 Cost evaluation for many-core microprocessor designs -- 8.2.1 Cost evaluation with homogeneous partitioning -- 8.2.2 Cost evaluation with heterogeneous partitioning --
9. Conclusion -- Bibliography -- Authors' biographies
Abstract freely available; full-text restricted to subscribers or individual document purchasers
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The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, promise attractive solutions to reduce the delay of interconnects in future microprocessors. 3D memory stacking enables much higher memory bandwidth for future chip-multiprocessor design, mitigating the "memory wall" problem. In addition, heterogenous integration enabled by 3D technology can also result in innovative designs for future microprocessors. This book first provides a brief introduction to this emerging technology, and then presents a variety of approaches to designing future 3D microprocessor systems, by leveraging the benefits of low latency, high bandwidth, and heterogeneous integration capability which are offered by 3D technology
Also available in print
Mode of access: World Wide Web
System requirements: Adobe Acrobat Reader
Title from PDF title page (viewed on June 20, 2015)
Link Print version: 9781627057653
Subject Three-dimensional integrated circuits
Computer architecture
emerging technology
die-stacking
3D integrated circuits
memory architecture
heterogeneous integration
Alt Author Zhao, Jishen., author