LEADER 00000nam  2200421   4500 
001    AAI3434493 
005    20111013150259.5 
008    111013s2010    ||||||||||||||||| ||eng d 
020    9781124413594 
035    (UMI)AAI3434493 
040    UMI|cUMI 
100 1  Patel, Kimish 
245 10 Energy efficient design and provisioning of hardware 
       resources in modern computing systems 
300    173 p 
500    Source: Dissertation Abstracts International, Volume: 72-
       02, Section: B, page: 1080 
500    Adviser: Massoud Pedram 
502    Thesis (Ph.D.)--University of Southern California, 2010 
520    Importance of energy efficiency in electronic systems is 
       ever increasing, from embedded systems such as smart 
       phones to large scale distributed systems such as 
       datacenters. Modern battery-powered, embedded systems are 
       complex devices providing various functionalities while 
       supporting a wide range of applications, leading to 
       complex energy profile and necessitating energy efficient 
       design for longer battery life. On the other end of the 
       spectrum lie the complex large-scale distributed systems 
       such as data centers. Such systems consume not only 
       significant computing power but also cooling power in 
       order to remove the heat generated by the information 
       technology equipment. The issue of energy efficiency in 
       such systems can be addressed at various levels of system 
       design, e.g., circuit/architecture level design time 
       solutions or operating system/application level runtime 
       solutions. In this thesis, we present circuit and 
       architecture level design time solutions for modern 
       microprocessors based on the concept of charge sharing, a 
       technique that is applicable to all kinds of systems 
       independent of the usage scenario, and system level run 
       time solutions based on energy-aware resource allocation 
       that is mostly applicable to data centers 
520    At the circuit level, we introduce a charge recycling 
       based optimization approach for 1) write operation power 
       minimization in on-chip memory structures with dedicated 
       write ports, such as register file, issue queue, reorder 
       buffer, etc., where charge among bit-lines is recycled in 
       order to reduce voltage swing on bit-lines and 2) power 
       minimization in off-chip data buses by recycling charge in
       a sequential manner where charge from bus lines 
       experiencing falling transitions is recycled to bus lines 
       with rising transitions, in multiple charge sharing cycles,
       so as to recycle more charge compared to simultaneous 
       charge recycling techniques 
520    Extending the idea of charge recycling to data caches with
       shared read write ports, we describe a new cache 
       architecture that can dynamically switch between the 
       charge sharing based write operation mode and regular 
       cache operation mode. At architecture level, we employ a 
       clustered store retirement technique, to delay the 
       instruction retirement for store operations, in order to 
       group stores together to generate back-to-back cache 
       writes so that the writes can take advantage of the 
       underlying circuit support for charge recycling to reduce 
       the write operation power 
520    The aforementioned design time solutions are equally 
       applicable independent of the workloads system is running 
       under. At a level higher where the underlying system 
       design is fixed, we employ, for given set of workloads and
       hardware resources, intelligent resource allocation to 
       achieve energy efficient resource assignment in large 
       scale distributed systems such as hosting centers. 
       Heterogeneity present among the servers in such large 
       scale distributed systems along with non energy 
       proportional behavior of these servers make the task of 
       resource allocation non-trivial. Using generalized 
       networks we capture power and performance heterogeneity 
       among servers while modeling utilization dependent non 
       energy proportional behavior. We present a generalized 
       network flow based resource allocation algorithm that, 
       where nodes represent workloads and resources, finds close
       -to-optimal solution in the presence of resource 
       heterogeneity and non energy proportionality, while 
       meeting the stipulated service level agreements (SLAs) 
590    School code: 0208 
650  4 Engineering, Computer 
650  4 Engineering, Electronics and Electrical 
650  4 Computer Science 
690    0464 
690    0544 
690    0984 
710 2  University of Southern California.|bElectrical Engineering
773 0  |tDissertation Abstracts International|g72-02B 
856 40 |uhttp://pqdd.sinica.edu.tw/twdaoapp/servlet/