LEADER 00000nam  2200325   4500 
001    AAI3444690 
005    20111201132955.5 
008    111201s2010    ||||||||||||||||| ||eng d 
020    9781124528205 
035    (UMI)AAI3444690 
040    UMI|cUMI 
100 1  Patel, Pratik Ashvin 
245 10 Steep Turn On/Off "Green" Tunnel Transistors 
300    104 p 
500    Source: Dissertation Abstracts International, Volume: 72-
       05, Section: B, page: 2994 
500    Adviser: Chenming Hu 
502    Thesis (Ph.D.)--University of California, Berkeley, 2010 
520    Scaling of supply voltage Vdd has significantly slowed 
       down since the 130 nm node. As a result, integrated 
       circuit (IC) power consumption has been on the rapid rise.
       This presents a serious thermal management challenge and 
       potential limiter of integration density as well as a 
       rapidly growing portion of the world electricity demand. 
       The problem lies in the 60 mV/dec swing limitation of any 
       device involving charge flow over energy barrier (i.e., 
       current state of art CMOS). This requires at least 60 mV 
       to decrease the transistor current by 10X. The future low 
       power or "green" energy efficient scenario would benefit 
       from a device that is friendlier to Vdd scaling. A 
       transistor where carriers tunnel through rather than flow 
       over a barrier is not subject to this limitation. However,
       achieving sub 60 mV/dec at current ranges of interest and 
       over many decades is not trivial when relying solely on 
       transmission probability modulation (i.e., increase/
       decrease of tunnel barrier width). Instead, if the absence
       /presence of tunneling state overlap is exploited a sharp 
       "off" to "on" transition is achievable. By engineering the
       transistor device structure such that this overlap (i.e., 
       onset of tunneling) occurs in a region of high electric 
       field results in steep sub 60 mV/dec response over many 
       decades of current. One novel design utilizes heavily 
       doped, ultra shallow N+/P+ junctions to achieve this 
       "sudden tunneling overlap" effect. Another design involves
       use of ultra thin body silicon-on-insulator (5 nm) to 
       achieve a similar effect. Simulation results show sub 500 
       mV Vdd is possible if suitable low-E g material is 
       introduced. Both designs have been fabricated in silicon 
       and their measurement results are presented 
590    School code: 0028 
650  4 Engineering, Electronics and Electrical 
690    0544 
710 2  University of California, Berkeley.|bElectrical 
       Engineering & Computer Sciences 
773 0  |tDissertation Abstracts International|g72-05B 
856 40 |uhttp://pqdd.sinica.edu.tw/twdaoapp/servlet/