LEADER 00000nam  2200673 i 4500 
001    7123242 
005    20150620133116.0 
006    m    eo  d         
007    cr cn |||m|||a 
008    150620s2015    caua   foab   000 0 eng d 
020    9781627057660|qebook 
020    |z9781627057653|qprint 
024 7  10.2200/S00644ED1V01Y201505CAC031|2doi 
035    (CaBNVSL)swl00405129 
035    (OCoLC)911246025 
040    CaBNVSL|beng|erda|cCaBNVSL|dCaBNVSL|dAS|dIIS 
050  4 TK7874.893|b.X543 2015 
082 04 621.3815|223 
100 1  Xie, Yuan,|d1973-,|eauthor 
245 10 Die-stacking architecture /|cYuan Xie, Jishen Zhao 
264  1 San Rafael, California (1537 Fourth Street, San Rafael, CA
       94901 USA) :|bMorgan & Claypool,|c2015 
300    1 online resource (xiii, 113 pages) :|billustrations 
336    text|2rdacontent 
337    electronic|2isbdmedia 
338    online resource|2rdacarrier 
490 1  Synthesis lectures on computer architecture,|x1935-3243 ;
       |v# 31 
500    Part of: Synthesis digital library of engineering and 
       computer science 
504    Includes bibliographical references (pages 99-111) 
505 0  1. 3D integration technology -- 1.1 3D integrated circuits
       vs. 3D packaging -- 1.2 Different process technologies for
       3D ICs -- 1.3 The impact of 3D technology on 3D 
       microprocessor partitioning -- 
505 8  2. Benefits of 3D integration -- 2.1 Wire length reduction
       -- 2.2 Memory bandwidth improvement -- 2.3 Heterogenous 
       integration -- 2.4 Cost-effective architecture -- 
505 8  3. Fine-granularity 3D processor design -- 3.1 3D cache 
       partitioning -- 3.1.1 3D cache partitioning strategies -- 
       3.1.2 Design exploration using 3DCacti -- 3.2 3D 
       Partitioning for logic blocks -- 
505 8  4. Coarse-granularity 3D processor design -- 4.1 3D Caches
       stacking -- 4.2 3D Main memory stacking -- 4.3 3D On-chip 
       stacked memory: cache or main memory? -- 4.3.1 On-chip 
       main memory -- 4.3.2 3D-stacked LLC -- 4.3.3 Dynamic 
       approach -- 4.4 PicoServer -- 
505 8  5. 3D GPU architecture -- 5.1 3D-stacked GPU memory -- 5.2
       3D-stacked GPU processor -- 
505 8  6. 3D network-on-chip -- 6.1 3D NoC router design -- 6.2 
       3D NoC topology design -- 6.3 3D optical NoC design -- 6.4
       Impact of 3D technology on NoC designs -- 
505 8  7. Thermal analysis and thermal-aware design -- 7.1 
       Thermal analysis -- 7.2 Thermal-aware floorplanning for 3D
       processors -- 7.3 Thermal-herding: thermal-aware 
       architecture design -- 
505 8  8. Cost analysis for 3D ICs -- 8.1 3D cost model -- 8.2 
       Cost evaluation for many-core microprocessor designs -- 
       8.2.1 Cost evaluation with homogeneous partitioning -- 
       8.2.2 Cost evaluation with heterogeneous partitioning -- 
505 8  9. Conclusion -- Bibliography -- Authors' biographies 
506    Abstract freely available; full-text restricted to 
       subscribers or individual document purchasers 
510 0  Compendex 
510 0  INSPEC 
510 0  Google scholar 
510 0  Google book search 
520 3  The emerging three-dimensional (3D) chip architectures, 
       with their intrinsic capability of reducing the wire 
       length, promise attractive solutions to reduce the delay 
       of interconnects in future microprocessors. 3D memory 
       stacking enables much higher memory bandwidth for future 
       chip-multiprocessor design, mitigating the "memory wall" 
       problem. In addition, heterogenous integration enabled by 
       3D technology can also result in innovative designs for 
       future microprocessors. This book first provides a brief 
       introduction to this emerging technology, and then 
       presents a variety of approaches to designing future 3D 
       microprocessor systems, by leveraging the benefits of low 
       latency, high bandwidth, and heterogeneous integration 
       capability which are offered by 3D technology 
530    Also available in print 
538    Mode of access: World Wide Web 
538    System requirements: Adobe Acrobat Reader 
588    Title from PDF title page (viewed on June 20, 2015) 
650  0 Three-dimensional integrated circuits 
650  0 Computer architecture 
653    emerging technology 
653    die-stacking 
653    3D integrated circuits 
653    memory architecture 
653    heterogeneous integration 
700 1  Zhao, Jishen.,|eauthor 
776 08 |iPrint version:|z9781627057653 
830  0 Synthesis digital library of engineering and computer 
       science 
830  0 Synthesis lectures in computer architecture ;|v# 31.|x1935
       -3243 
856 41 |zeBook(IEEE-MORGAN)|uhttp://ieeexplore.ieee.org/servlet/
       opac?bknumber=7123242"