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Author Rajsuman, Rochit
Title System-on-a-chip : Design And Test
Imprint Norwood : Artech House, 2000
©2000
book jacket
Descript 1 online resource (289 pages)
text txt rdacontent
computer c rdamedia
online resource cr rdacarrier
Note Intro -- Contents v -- Preface xi -- Acknowledgment xiii -- Part I: Design 1 -- 1 Introduction 3 -- 1.1 Architecture of the Present-Day SoC 5 -- 1.2 Design Issues of SoC 8 -- 1.3 Hardware-Software Codesign 14 -- 1.4 Core Libraries, EDA Tools, and Web Pointers 21 -- References 29 -- 2 Design Methodology for Logic Cores 33 -- 2.1 SoC Design Flow 34 -- 2.2 General Guidelines for Design Reuse 36 -- 2.3 Design Process for Soft and Firm Cores 43 -- 2.4 Design Process for Hard Cores 47 -- 2.5 Sign-Off Checklist and Deliverables 51 -- 2.6 System Integration 53 -- References 55 -- 3 Design Methodology for Memory and Analog Cores 57 -- 3.1 Why Large Embedded Memories 57 -- 3.2 Design Methodology for Embedded Memories 59 -- 3.3 Specifications of Analog Circuits 72 -- 3.4 High-Speed Circuits 79 -- References 83 -- 4 Design Validation 85 -- 4.1 Core-Level Validation 86 -- 4.2 Core Interface Verification 93 -- 4.3 SoC Design Validation 95 -- Reference 103 -- 5 Core and SoC Design Examples 105 -- 5.1 Microprocessor Cores 105 -- 5.2 Comments on Memory Core Generators 112 -- 5.3 Core Integration and On-Chip Bus 113 -- 5.4 Examples of SoC 115 -- References 122 -- Part II: Test 123 -- 6 Testing of Digital Logic Cores 125 -- 6.1 SoC Test Issues 126 -- 6.2 Access, Control, and Isolation 128 -- 6.3 IEEE P1500 Effort 129 -- 6.4 Core Test and IP Protection 138 -- 6.5 Test Methodology for Design Reuse 142 -- 6.6 Testing of Microprocessor Cores 144 -- References 152 -- 7 Testing of Embedded Memories 155 -- 7.1 Memory Fault Models and Test Algorithms 156 -- 7.2 Test Methods for Embedded Memories 162 -- 7.3 Memory Redundancy and Repair 171 -- 7.4 Error Detection and Correction Codes 175 -- 7.5 Production Testing of SoC With Large Embedded Memory 176 -- References 177
8 Testing of Analog and Mixed-Signal Cores 181 -- 8.1 Analog Parameters and Characterization 182 -- 8.2 Design-for-Test and Built-in Self-Test Methods for Analog Cores 191 -- 8.3 Testing of Specific Analog Circuits 200 -- References 204 -- 9 Iddq Testing 207 -- 9.1 Physical Defects 207 -- 9.2 Iddq Testing Difficulties in SoC 219 -- 9.3 Design-for-Iddq-Testing 115 -- 9.4 Design Rules for Iddq Testing 230 -- 9.5 Iddq Test Vector Generation 231 -- References 236 -- 10 Production Testing 239 -- 10.1 Production Test Flow 239 -- 10.2 At-Speed Testing 241 -- 10.3 Production Throughput and Material Handling 246 -- References 249 -- 11 Summary and Conclusions 251 -- 11.1 Summary 251 -- 11.2 Future Scenarios 254 -- Appendix: RTL Guidelines for Design Reuse 257 -- A.1 Naming Convention 257 -- A.2 General Coding Guidelines 258 -- A.3 RTL Development for Synthesis 260 -- A.4 RTL Checks 262 -- About the Author 265 -- Index 267
Starting with a basic overview of system-on-a-chip (SoC) including definitions of related terms, this text explains SoC design challenges, together with developments in SoC design and and test methodologies
Description based on publisher supplied metadata and other sources
Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2020. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries
Link Print version: Rajsuman, Rochit System-on-a-chip : Design And Test Norwood : Artech House,c2000 9781580531078
Subject Embedded computer systems -- Design and construction.;Embedded computer systems -- Testing.;Application specific integrated circuits -- Design and construction
Electronic books
Alt Author Ling, Hao
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