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Author Larus, James R
Title Transactional memory [electronic resource] / James R. Larus and Ravi Rajwar
Imprint San Rafael, Calif (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool Publishers, 2006
book jacket
Edition 1st ed
Descript 1 electronic text (xiii, 211 p. : ill.) : digital file
Series Synthesis lectures on computer architecture, 1935-3243 ; #2
Synthesis lectures on computer architecture (Online) ; #2
Note Part of: Synthesis digital library of engineering and computer science
Title from PDF t.p. (viewed on Nov. 7, 2008)
Series from website
Includes bibliographical references
Introduction -- Programming transactional memory -- Software transactional memory -- Hardware-supported transactional memory -- Conclusions
Abstract freely available; full-text restricted to subscribers or individual document purchasers
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Mode of access: World Wide Web
System requirements: Adobe Acrobat Reader
The advent of multicore processors has renewed interest in the idea of incorporating transactions into the programming model used to write parallel programs. This approach, known as transactional memory, offers an alternative, and hopefully better, way to coordinate concurrent threads. The ACI (atomicity, consistency, isolation) properties of transactions provide a foundation to ensure that concurrent reads and writes of shared data do not produce inconsistent or incorrect results. At a higher level, a computation wrapped in a transaction executes atomically either it completes successfully and commits its result in its entirety or it aborts. In addition, isolation ensures the transaction produces the same result as if no other transactions were executing concurrently. Although transactions are not a parallel programming panacea, they shift much of the burden of synchronizing and coordinating parallel computations from a programmer to a compiler, runtime system, and hardware. The challenge for the system implementers is to build an efficient transactional memory infrastructure. This book presents an overview of the state of the art in the design and implementation of transactional memory systems, as of early summer 2006
Also available in print
Subject Transactional systems (Computer systems)
Threads (Computer programs)
Parallel programming (Computer science)
Transactional memory
Parallel programming concurrent programming
Programming languages
Computer architecture
Computer hardware
Wait-free data structures
Cache coherence
Alt Author Rajwar, Ravi
Vari Title Synthesis digital library of engineering and computer science
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