Record:   Prev Next
Author Meinerzhagen, Pascal, author
Title Gain-cell embedded DRAMs for low-power VLSI systems-on-chip / by Pascal Meinerzhagen, Adam Teman, Robert Giterman, Noa Edri, Andreas Burg, Alexander Fish
Imprint Cham : Springer International Publishing : Imprint: Springer, 2018
book jacket
Descript 1 online resource (ix, 146 pages) : illustrations, digital ; 24 cm
text txt rdacontent
computer c rdamedia
online resource cr rdacarrier
text file PDF rda
Note Motivation -- Introduction to Gain-Cell Based eDRAMs (GC-eDRAMs) -- GC-eDRAMs Operated at Scaled Supply Voltages -- Near-VT GC-eDRAM Implementations with Extended Retention Times -- Aggressive Technology and Voltage Scaling (to Sub-VT Domain) -- Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications -- 4T Gain-Cell with Internal-Feedback for Ultra-Low Retention Power at Scaled CMOS Nodes -- Multilevel GC-eDRAM (MLGC-eDRAM) -- Soft Error Tolerant Low Power 4T Gain-Cell Array with Multi-Bit Error Detection and Correction -- Conclusions
This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs) Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy
Host Item Springer eBooks
Subject Embedded computer systems
Systems on a chip
Integrated circuits -- Very large scale integration
Engineering
Circuits and Systems
Memory Structures
Electronics and Microelectronics, Instrumentation
Alt Author Teman, Adam, author
Giterman, Robert, author
Edri, Noa, author
Burg, Andreas, author
Fish, Alexander, author
SpringerLink (Online service)
Record:   Prev Next