| 說明 |
130 p |
| 附註 |
Source: Dissertation Abstracts International, Volume: 66-02, Section: B, page: 1062 |
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Chair: Jan Rabaey |
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Thesis (Ph.D.)--University of California, Berkeley, 2004 |
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Synchronization is increasingly important in wireless communication devices. Synchronization performance is critical to system performance and, it is where a large amount of design time and receiver area and power is spent |
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Not only is synchronization important, but the relevance is increasing due to four factors: (1) Decreased transmit distances use lower transmit power and, therefore, receiver power begins to dominate. (2) The wireless channel is more frequency selective at higher transmission speeds which require increased synchronization functionality. (3) Trends toward higher bandwidth efficiency moves modulation to higher order constellations where synchronization specifications are tighter. (4) The push for integration moves RF functionality to digital CMOS processes with low supply voltages forcing the synchronization system to contend with more front-end nonidealities |
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There are few places where the whole topic of synchronization is covered and fewer still where the power consumption is considered. This research shows that significant system power savings can be realized through systematic exploration of synchronization power consumption |
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This dissertation sets up a framework for the systematic exploration of power consumption in synchronization systems, applies this framework to a few representative problems, and uses some system examples to show the impact of this type of exploration |
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At the component level, frequency estimation and interpolation are investigated. It is shown that frequency estimation power reductions of up to 4x are possible while simultaneously decreasing convergence time by up to 4x. For interpolation, it is shown that proper parameter selection can result in a 10x reduction in power consumption |
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At the system level, two non standards-based communication systems are considered. PNII is a 1.6 Mbps personal area network system for wireless intercom type applications over short distances (10--30 m). The original system's frequency and phase estimation blocks are redesigned using the framework developed here. Simultaneous reductions of 66% in synchronization energy consumption and 72% in convergence time are achieved. PN3 is a 50 Kbps system designed for use in wireless sensor network applications. A 300uW synchronization system was designed for PN3. This is low enough so that further reduction has very little impact on system energy consumption |
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School code: 0028 |
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DDC |
| Host Item |
Dissertation Abstracts International 66-02B
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| 主題 |
Engineering, Electronics and Electrical
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0544
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| Alt Author |
University of California, Berkeley
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