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作者 Wang, Laung-Terng
書名 VLSI Test Principles and Architectures : Design for Testability
出版項 San Francisco : Elsevier Science & Technology, 2006
©2006
國際標準書號 9780080474793 (electronic bk.)
9780123705976
book jacket
版本 1st ed
說明 1 online resource (809 pages)
text txt rdacontent
computer c rdamedia
online resource cr rdacarrier
系列 Morgan Kaufmann Series in Systems on Silicon
Morgan Kaufmann Series in Systems on Silicon
附註 Front Cover -- VLSI Test Principles and Architectures: Design for Testability -- Copyright -- Contents -- Preface -- In the Classroom -- Acknowledgments -- Contributors -- About the Editors -- Chapter 1: Introduction -- Importance of Testing -- Testing During the VLSI Lifecycle -- VLSI Development Process -- Design Verification -- Yield and Reject Rate -- Electronic System Manufacturing Process -- System-Level Operation -- Challenges in VLSI Testing -- Test Generation -- Fault Models -- Stuck-At Faults -- Transistor Faults -- Open and Short Faults -- Delay Faults and Crosstalk -- Pattern Sensitivity and Coupling Faults -- Analog Fault Models -- Levels of Abstraction in VLSI Testing -- Register-Transfer Level and Behavioral Level -- Gate Level -- Switch Level -- Physical Level -- Historical Review of VLSI Test Technology -- Automatic Test Equipment -- Automatic Test Pattern Generation -- Fault Simulation -- Digital Circuit Testing -- Analog and Mixed-Signal Circuit Testing -- Design for Testability -- Board Testing -- Boundary Scan Testing -- Concluding Remarks -- Exercises -- Acknowledgments -- References -- Chapter 2: Design for Testability -- Introduction -- Testability Analysis -- SCOAP Testability Analysis -- Combinational Controllability and Observability Calculation -- Sequential Controllability and Observability Calculation -- Probability-Based Testability Analysis -- Simulation-Based Testability Analysis -- RTL Testability Analysis -- Design for Testability Basics -- Ad Hoc Approach -- Test Point Insertion -- Structured Approach -- Scan Cell Designs -- Muxed-D Scan Cell -- Clocked-Scan Cell -- LSSD Scan Cell -- Scan Architectures -- Full-Scan Design -- Muxed-D Full-Scan Design -- Clocked Full-Scan Design -- LSSD Full-Scan Design -- Partial-Scan Design -- Random-Access Scan Design -- Scan Design Rules -- Tristate Buses
Bidirectional I/O Ports -- Gated Clocks -- Derived Clocks -- Combinational Feedback Loops -- Asynchronous Set/Reset Signals -- Scan Design Flow -- Scan Design Rule Checking and Repair -- Scan Synthesis -- Scan Configuration -- Scan Replacement -- Scan Reordering -- Scan Stitching -- Scan Extraction -- Scan Verification -- Verifying the Scan Shift Operation -- Verifying the Scan Capture Operation -- Scan Design Costs -- Special-Purpose Scan Designs -- Enhanced Scan -- Snapshot Scan -- Error-Resilient Scan -- RTL Design for Testability -- RTL Scan Design Rule Checking and Repair -- RTL Scan Synthesis -- RTL Scan Extraction and Scan Verification -- Concluding Remarks -- Exercises -- Acknowledgments -- References -- Chapter 3: Logic and Fault Simulation -- Introduction -- Logic Simulation for Design Verification -- Fault Simulation for Test and Diagnosis -- Simulation Models -- Gate-Level Network -- Sequential Circuits -- Logic Symbols -- Unknown State u -- High-Impedance State Z -- Intermediate Logic States -- Logic Element Evaluation -- Truth Tables -- Input Scanning -- Input Counting -- Parallel Gate Evaluation -- Timing Models -- Transport Delay -- Inertial Delay -- Wire Delay -- Functional Element Delay Model -- Logic Simulation -- Compiled-Code Simulation -- Logic Optimization -- Logic Levelization -- Code Generation -- Event-Driven Simulation -- Nominal-Delay Event-Driven Simulation -- Compiled-Code Versus Event-Driven Simulation -- Hazards -- Static Hazard Detection -- Dynamic Hazard Detection -- Fault Simulation -- Serial Fault Simulation -- Parallel Fault Simulation -- Parallel Fault Simulation -- Parallel-Pattern Fault Simulation -- Deductive Fault Simulation -- Concurrent Fault Simulation -- Differential Fault Simulation -- Fault Detection -- Comparison of Fault Simulation Techniques -- Alternatives to Fault Simulation -- Toggle Coverage
Fault Sampling -- Critical Path Tracing -- Statistical Fault Analysis -- Concluding Remarks -- Exercises -- References -- Chapter 4: Test Generation -- Introduction -- Random Test Generation -- Exhaustive Testing -- Theoretical Background: Boolean Difference -- Untestable Faults -- Designing a Stuck-At ATPG for Combinational Circuits -- A Naive ATPG Algorithm -- Backtracking -- A Basic ATPG Algorithm -- D Algorithm -- PODEM -- FAN -- Static Logic Implications -- Dynamic Logic Implications -- Designing a Sequential ATPG -- Time Frame Expansion -- 5-Valued Algebra Is Insufficient -- Gated Clocks and Multiple Clocks -- Untestable Fault Identification -- Multiple-Line Conflict Analysis -- Designing a Simulation-Based ATPG -- Overview -- Genetic-Algorithm-Based ATPG -- Issues Concerning the GA Population -- Issues Concerning GA Parameters -- Issues Concerning the Fitness Function -- CASE Studies -- Advanced Simulation-Based ATPG -- Seeding the GA with Helpful Sequences -- Logic-Simulation-Based ATPG -- Spectrum-Based ATPG -- Hybrid Deterministic and Simulation-Based ATPG -- ALT-TEST Hybrid -- ATPG for Non-Stuck-At Faults -- Designing an ATPG That Captures Delay Defects -- Classification of Path-Delay Faults -- ATPG for Path-Delay Faults -- ATPG for Transition Faults -- Transition ATPG Using Stuck-At ATPG -- Transition ATPG Using Stuck-At Vectors -- Transition Test Chains via Weighted Transition Graph -- Bridging Fault ATPG -- Other Topics in Test Generation -- Test Set Compaction -- N-Detect ATPG -- ATPG for Acyclic Sequential Circuits -- IDDQ Testing -- Designing a High-Level ATPG -- Concluding Remarks -- Exercises -- References -- Chapter 5: Logic Built-In Self-Test -- Introduction -- BIST Design Rules -- Unknown Source Blocking -- Analog Blocks -- Memories and Non-Scan Storage Elements -- Combinational Feedback Loops -- Asynchronous Set/Reset Signals
Tristate Buses -- False Paths -- Critical Paths -- Multiple-Cycle Paths -- Floating Ports -- Bidirectional I/O Ports -- Re-Timing -- Test Pattern Generation -- Exhaustive Testing -- Binary Counter -- Complete LFSR -- Pseudo-Random Testing -- Maximum-Length LFSR -- Weighted LFSR -- Cellular Automata -- Pseudo-Exhaustive Testing -- Verification Testing -- Segmentation Testing -- Delay Fault Testing -- Summary -- Output Response Analysis -- Ones Count Testing -- Transition Count Testing -- Signature Analysis -- Serial Signature Analysis -- Parallel Signature Analysis -- Logic BIST Architectures -- BIST Architectures for Circuits without Scan Chains -- A Centralized and Separate Board-Level BIST Architecture -- Built-In Evaluation and Self-Test (BEST) -- BIST Architectures for Circuits with Scan Chains -- LSSD On-Chip Self-Test -- Self-Testing Using MISR and Parallel SRSG -- BIST Architectures Using Register Reconfiguration -- Built-In Logic Block Observer -- Modified Built-In Logic Block Observer -- Concurrent Built-In Logic Block Observer -- Circular Self-Test Path (CSTP) -- BIST Architectures Using Concurrent Checking Circuits -- Concurrent Self-Verification -- Summary -- Fault Coverage Enhancement -- Test Point Insertion -- Test Point Placement -- Control Point Activation -- Mixed-Mode BIST -- ROM Compression -- LFSR Reseeding -- Embedding Deterministic Patterns -- Hybrid BIST -- BIST Timing Control -- Single-Capture -- One-Hot Single-Capture -- Staggered Single-Capture -- Skewed-Load -- One-Hot Skewed-Load -- Aligned Skewed-Load -- Staggered Skewed-Load -- Double-Capture -- One-Hot Double-Capture -- Aligned Double-Capture -- Staggered Double-Capture -- Fault Detection -- A Design Practice -- BIST Rule Checking and Violation Repair -- Logic BIST System Design -- Logic BIST Architecture -- TPG and ORA -- Test Controller -- Clock Gating Block
Re-Timing Logic -- Fault Coverage Enhancing Logic and Diagnostic Logic -- RTL BIST Synthesis -- Design Verification and Fault Coverage Enhancement -- Concluding Remarks -- Exercises -- Acknowledgments -- References -- Chapter 6: Test Compression -- Introduction -- Test Stimulus Compression -- Code-Based Schemes -- Dictionary Code (Fixed-to-Fixed) -- Huffman Code (Fixed-to-Variable) -- Run-Length Code (Variable-to-Fixed) -- Golomb Code (Variable-to-Variable) -- Linear-Decompression-Based Schemes -- Combinational Linear Decompressors -- Fixed-Length Sequential Linear Decompressors -- Variable-Length Sequential Linear Decompressors . -- Combined Linear and Nonlinear Decompressors -- Broadcast-Scan-Based Schemes -- Broadcast Scan -- Illinois Scan -- Multiple-Input Broadcast Scan -- Reconfigurable Broadcast Scan -- Virtual Scan -- Test Response Compaction -- Space Compaction -- Zero-Aliasing Linear Compaction -- X-Compact -- X-Blocking -- X-Masking -- X-Impact -- Time Compaction -- Mixed Time and Space Compaction -- Industry Practices -- OPMISR+ -- Embedded Deterministic Test -- VirtualScan and UltraScan -- Adaptive Scan -- ETCompression -- Summary -- Concluding Remarks -- Exercises -- Acknowledgments -- References -- Chapter 7: Logic Diagnosis -- Introduction -- Combinational Logic Diagnosis -- Cause-Effect Analysis -- Compaction and Compression of Fault Dictionary -- Effect-Cause Analysis -- Structural Pruning -- Backtrace Algorithm -- Inject-and-Evaluate Paradigm -- Chip-Level Strategy -- Direct Partitioning -- Two-Phase Strategy -- Overall Chip-Level Diagnostic Flow -- Diagnostic Test Pattern Generation -- Summary of Combinational Logic Diagnosis -- Scan Chain Diagnosis -- Preliminaries for Scan Chain Diagnosis -- Hardware-Assisted Method -- Modified Inject-and-Evaluate Paradigm -- Signal-Profiling-Based Method -- Diagnostic Test Sequence Selection
Run-and-Scan Test Application
The most up-to-date coverage available of VLSI Testing and Design-for-Testability!
Description based on publisher supplied metadata and other sources
Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2020. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries
鏈接 Print version: Wang, Laung-Terng VLSI Test Principles and Architectures : Design for Testability San Francisco : Elsevier Science & Technology,c2006 9780123705976
主題 Integrated circuits - Very large scale integration - Design
Electronic books
Alt Author Wu, Cheng-Wen
Wen, Xiaoqing
Abdel-Hafez, Khader S
Bhattacharya, Soumendu
Chatterjee, Abhijit
Chen, Xinghao
Cheng, Kwang-Ting
Eklow, William
Hsiao, Michael S
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