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作者 Hodjat, Alireza
書名 HW/SW co-design and ASIP architectures for cryptographic primitives in embedded security systems
國際標準書號 9780542567049
book jacket
說明 156 p
附註 Source: Dissertation Abstracts International, Volume: 67-02, Section: B, page: 1053
Adviser: Ingrid Verbauwhede
Thesis (Ph.D.)--University of California, Los Angeles, 2005
The world is becoming more and more connected because of the extensive use of embedded systems. However, due to the fact that embedded devices are easily accessible to an adversary, security needs to be taken into account in the design process of such embedded systems. There is a variety of hardware/software architectural and micro-architectural choices as well as the implementation platforms used for security primitives. Each of these choices affects the overall performance, area cost, and the ability to resist against the side-channel attacks
This dissertation presents different hardware/software co-design architectures and design methods for cryptographic-based Application Specific Instruction Set coprocessors which are suitable for secure embedded systems. The architectural design space is divided into four different types of micro-architectures. These are: pure software for embedded processor cores, hardware/software co-design architectures which include an embedded processor core as well as a hardware accelerator, an Application Specific Instruction Set Processors or coprocessors (ASIP), and pure hardware (ASIC) architectures
In this dissertation, the two most recent public-key and secret key cryptographic algorithms are analyzed over the architectural design space using the Standard Cell and FPGA implementation platforms. Depending on the application the optimization is performed for different metrics such as resource usage and area cost, delay and throughput, or the ability for being resistant against the side-channel attacks
The first part of this dissertation is dedicated to the Elliptic Curve (ECC) and Hyper-elliptic Curve (HECC) public-key cryptosystems. It explores a detailed analysis for pure software, HW/SW co-design, ASIP architecture, and pure hardware implementations using the FPGA platforms. The research contribution in this part is to show that for ECC and HECC algorithms the software only solution is not an option in the constrained environments; however, by adding some limited hardware resources one can obtain an attractive performance. Moreover, the comparison between ECC and HECC implementations shows that, for the first time, performance results for HECC are faster while at the same time require less extra hardware
The second part of this dissertation is about the Advanced Encryption Standard (AES) algorithm. In this section, first an Application Specific Instruction Set coprocessor is presented which is based on a non-pipelined AES architecture for both FPGA and Standard Cell platforms. (Abstract shortened by UMI.)
School code: 0031
Host Item Dissertation Abstracts International 67-02B
主題 Engineering, Electronics and Electrical
Computer Science
Alt Author University of California, Los Angeles
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