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作者 Prakash, Amit
書名 Architectures and algorithms for high performance switching
國際標準書號 0496014226
book jacket
說明 84 p
附註 Source: Dissertation Abstracts International, Volume: 65-08, Section: B, page: 4201
Supervisor: Adnan Aziz
Thesis (Ph.D.)--The University of Texas at Austin, 2004
Switches are ubiquitous in modern computing, appearing in wide-area networks, multiprocessor servers, and data storage systems. With the advent of high-speed link technology, switches have become the bottleneck in moving data in the network. Existing switch architectures either require the interconnection network and packet buffers to work at a very high speed or require complex scheduling problems to be solved quickly. In this dissertation we investigate whether there are switch architectures that can support high-speed links that are simultaneously easy to schedule, and can be built out of inexpensive components
The approach we take is using parallelism to solve complex scheduling problems. We choose switching architectures such that the corresponding scheduling problem can be efficiently solved with a reasonable amount of hardware. In particular, we present two switch architectures for which we have developed efficient scheduling algorithms. The first switch achieves optimum throughput and optimum average latency while the second switch guarantees optimum throughput only but uses considerably less hardware
School code: 0227
DDC
Host Item Dissertation Abstracts International 65-08B
主題 Engineering, Electronics and Electrical
Computer Science
0544
0984
Alt Author The University of Texas at Austin
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