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作者 Proesel, Jonathan E
書名 Flash analog-to-digital converter design based on statistical post-silicon calibration
國際標準書號 9781124008394
book jacket
說明 118 p
附註 Source: Dissertation Abstracts International, Volume: 71-05, Section: B, page: 3257
Adviser: Lawrence T. Pileggi
Thesis (Ph.D.)--Carnegie Mellon University, 2010
High-speed (multi-GS/s), low- to mid-resolution (4- to 8-bit) analog-to-digital converters (ADCs) are required for many applications, such as high-speed wireless and wireline communications, digital oscilloscopes, and radar. The flash ADC architecture is commonly used to implement ADCs for such applications. Flash ADCs consist of a large bank of comparators operating in parallel and each comparator must meet a strict input-offset specification. To meet the input-offset specification with minimal power and area overhead, comparator calibration techniques are required
This work proposes the application of a new digital calibration technique, statistical element selection (SES). SES begins with a regular fabric of nominally identical but randomly varying circuit elements, such as individual devices (e.g., transistors) or multi-device subcircuits (e.g., differential pairs). The fabric is designed to be reconfigurable, allowing any subset of elements to be connected in parallel. By intelligently choosing a subset of elements to use, SES provides exponential decrease in offset standard deviation with respect to the total number of elements
Monte Carlo simulation results demonstrate SES and provide guidance for design efforts. Yield is shown to improve considerably faster than competing digital calibration techniques (DAC-based calibration, redundancy, and increased device sizing)
Two SES-based comparator designs are implemented in 65nm digital bulk CMOS. Silicon measurements verify the Monte Carlo simulation results and demonstrate significant improvements in offset standard deviation (14mV to 0.3mV) and yield (10.9% to 99.6%)
An 8-bit, 1.5GS/s flash ADC is implemented using the SES-based 65nm CMOS comparators. The performance is limited by comparator noise which degrades the effective number of bits (ENOB) from 7.5 bits to 5.8 bits. The ADC achieves a figure of merit (FoM) of 0.42pJ/conv, the best FoM reported for 1+GS/s, 7+-bit ADCs and among the top 10 FoMs for flash ADCs published from 2007--2009. The flash ADC measurement results demonstrate the efficiency and efficacy of SES
School code: 0041
Host Item Dissertation Abstracts International 71-05B
主題 Engineering, Electronics and Electrical
0544
Alt Author Carnegie Mellon University
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