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作者 Shenoy, Rohit S
書名 Technology and scaling of ultrathin body double-gate FETs
國際標準書號 0496135481
book jacket
說明 168 p
附註 Source: Dissertation Abstracts International, Volume: 65-11, Section: B, page: 5949
Adviser: Krishna C. Saraswat
Thesis (Ph.D.)--Stanford University, 2005
As silicon CMOS technology advances into the sub-50 nm regime, fundamental and manufacturing limits impede the traditional scaling of transistors. Innovations in materials and device structures are needed for continued transistor miniaturization with commensurate performance improvements. The enhanced electrostatic gate control over the channel makes the ultrathin body double-gate (DG) FET a leading candidate for replacing bulk CMOS transistors in future technology generations. This research is focused on some of the major issues in the design and fabrication of high performance scaled DG FETs
The first part of this research deals with extrinsic factors such as parasitic capacitance and resistance that limit the overall performance of ultrathin body DG FETs. In particular, the optimization of the lateral doping profile in the thin source/drain (S/D) extension regions to minimize series resistance is studied in detail and quantified by device simulation
Next, a novel process is proposed to fabricate a planar DG FET with the following attributes: (1) deposition-controlled uniform ultrathin body, (2) fully self-aligned gates for low parasitic capacitance, and (3) flared-out low resistance S/D regions. This process thus yields the ideal DG FET that satisfies intrinsic and extrinsic requirements for scalability. Experimental work on the process development is used to verify the feasibility of the key steps---(1) epitaxial CVD of high quality trilayer stacks of SiGe/Si/SiGe, (2) enhanced oxidation rate of SiGe with respect to Si, (3) isotropic etching of SiGe with high selectivity to Si, and (4) low resistance in-situ doped S/D formation. As proof of concept, functional double-gate transistors are demonstrated with very good turn-off characteristics (nearly ideal subthreshold swing and very low DIBL)
A new methodology has been developed (in collaboration with co-workers at Stanford University) to optimize the supply voltage, threshold voltage, and effective oxide thickness for minimizing the total power dissipation of digital logic transistors given an application and target delay. A framework has been developed by incorporating this concept for the comparison of future transistor structures and using optimized power-delay curves for benchmarking
School code: 0212
DDC
Host Item Dissertation Abstracts International 65-11B
主題 Engineering, Electronics and Electrical
0544
Alt Author Stanford University
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