Record:   Prev Next
作者 Tu, Shi-hsuan (Stefan)
書名 CMOS I/O study on latchup and ESD into the nanoscaling era with DFM considerations
國際標準書號 9780542870262
book jacket
說明 134 p
附註 Source: Masters Abstracts International, Volume: 45-01, page: 0427
Adviser: Robert K. F. Teng
Thesis (M.S.)--California State University, Long Beach, 2006
With CMOS transistors being scaled well into the nanometer regime, and IC designs becoming larger, faster and more complex, I/Os become a very important design factor. As daily consumer technology constantly requires more and more bandwidth and speed for multimedia applications, more and more industry leaders increase functionality while decreasing the size of the chip design. This thesis will begin with a study of commonly available PC bus standards followed by the theoretical research on the effects of nanoscaling on I/O design. A special emphasis will be put on traditional and recent latchup and electrostatic discharge (ESD) models. As performance and reliability of CMOS I/Os need to be maintained during fabrication, the Design for Manufacturability (DFM) concept is considered and explored
School code: 6080
DDC
Host Item Masters Abstracts International 45-01
主題 Engineering, Electronics and Electrical
0544
Alt Author California State University, Long Beach
Record:   Prev Next