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作者 Yu, Xiao Yan
書名 Design of power-efficient floating-point adder blocks
國際標準書號 9780549220732
book jacket
說明 87 p
附註 Source: Dissertation Abstracts International, Volume: 68-09, Section: B, page: 6209
Adviser: Vojm G. Oklobdzija
Thesis (Ph.D.)--University of California, Davis, 2007
The development of power-efficient floating-point adders for two different frequency requirements is presented. Our goal is to design frequency and application specific adders that will provide the best overall system performance
For high-frequency applications, a fast 128-bit floating-point adder is designed and fabricated as part of the POWER6 binary floating-point unit in IBM 65nm SOI process technology. Efficient use of static circuits, careful balance of the look-ahead tree and optimal partition of the adder blocks enable the floating-point unit to operate beyond 5GHz with 1.1 V supply
For medium frequency applications, a power and area efficient 108-bit floating-point adder is implemented using IBM 65nm SOI technology. Careful balances of the adder structure and structure-aware layout techniques enable our adder to have a latency of 270ps at power consumption of 2 0mW with 1V supply
School code: 0029
DDC
Host Item Dissertation Abstracts International 68-09B
主題 Engineering, Electronics and Electrical
0544
Alt Author University of California, Davis
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